Simulation of effects of single nuclear particles on a STGRS trigger with the separation of transistors into two groups

 
PIIS054412690002771-5-1
DOI10.31857/S054412690002771-5
Publication type Article
Status Published
Authors
Affiliation: Research Institute of System Studies of the Russian Academy of Sciences
Address: Russian Federation
Affiliation: National Research Nuclear University “MEPI”
Address: Russian Federation
Journal nameMikroelektronika
EditionVolume 47 6
Pages460-472
Abstract

  

Keywords
Received08.12.2018
Publication date08.12.2018
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1. Calin T., Nicolaidis M., Velazco R. Upset hardened memory design for submicron CMOS technology // IEEE Transactions on Nuclear Science. 1996. V. 43. № 6. P. 2874–2878

2. Loveless T. D., Jagannathan S., Reece T., Chetia J., Bhuva B. L., McCurdy M.W., Massengill L. W., Wen S.-J., Wong R., Rennie D. Neutron- and protoninduced single event upsets for D- and DICE-flip/flop designs at a 40 nm technology node // IEEE Transactions on Nuclear Science. 2011. V. 58. № 3. P. 1008–1014.

3. Lilja K., Bounasser M., Wen S., Wong R., Holst J., Gaspard N., Jagannathan S., Loveless D., Bhuva B. Single event performance and layout optimization of flip-flops in a 28-nm bulk technology // IEEE Transactions on Nuclear Science. 2013. V. 60. № 4. P. 2782–2788.

4. Katunin Yu. V., Stenin V. Ya., Stepanov P. V. Modelirovanie kharakteristik triggernykh ehlementov KMOP dvukhfaznoj logiki s uchetom razdeleniya zaryada pri vozdejstvii otdel'nykh yadernykh chastits // Mikroehlektronika. 2014. T. 43. № 2. S. 104–117.

5. Stenin V. Ya. M odelirovanie kharakteristik KMOP 28-nm yacheek DICE v nestatsionarnykh sostoyaniyakh, vyzvannykh vozdejstviem odinochnykh yadernykh chastits // Mikroehlektronika. 2015. T. 44. № 5. S. 368–379.

6. Stenin V. Ya., Katunin Yu. V., Stepanov P. V. Sboeustojchivye OZU na osnove STG DICE-ehlementov pamyati s razdelennymi na dve gruppy tranzistorami // Mikroehlektronika. 2016. T. 45. № 6. S. 456–470.

7. Katunin Yu. V., Stenin V. Ya. TCAD-modelirovanie ehffektov vozdejstviya odinochnykh yadernykh chastits na yachejki pamyati STG DICE // Mikroehlektronika. 2018. T. 47. № 1. S. 22–36.

8. Katunin Yu.V., Stenin V.Ya. The multiport CMOS memory cell based on the DICE trigger with two spaced transistor groups for hardened 65-nm CMOS SRAM // Proceedings ofInternational Siberian Conference on Control and Communications. Moscow. 2016. P. 1–5.

9. Katunin Yu. V., Stenin V.Ya. The STG DICE cell with the decoder for reading data in steady and unsteady states for hardened SRAM // in Proc. of RADECS. Geneva. Switzerland. Oct. 2017. P. 1–8.

10. Stenin V.Ya., Antonyuk A. V. Design of the CMOS Comparison Elements on STG DICE for a Content-Addressable Memory and Simulation of Single-Event Transients // Telfor Journal. 2017. V. 9. № 1. P. 61– 66.

11. Katunin Yu.V., Stenin V.Ya. TCAD Simulation of Single-Event Transients in the 65-nm CMOS Element of Matching for a Content-Addressable Memory // Proceedings of Telecommunications Forum. TELFOR–25. Belgrad. Serbia. Nov. 2017. P. 1–4.

12. Stenin V. Ya., Stepanov P. V. Bazovye ehlementy pamyati na osnove yacheek DICE dlya sboe ustojchivykh KMOP 28 nm OZU // Mikroehlektronika. 2015. T. 44. № 6. S. 416–427.

13. Stenin V.Ya., Antonyuk A. V., KatuninYu.V., Stepanov P. V. Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects // Proceedings of International Siberian Conference on Control and Communications. Astana. Kazakhstan. Jun. 2017. P. 1–6.

14. Stenin V. Ya., Antonyuk A. V., Stepanov P. V., Katunin Yu.V. Design of the 65-nm CMOS translation lookaside buffer on the hardened elements// Proceedings of Telecommunications Forum.TELFOR-25. Belgrad. Serbia. Nov. 2017. P. 1–4.

15. Wang W., Gong H. Edge triggered pulse latch designed with delayed latching edge for radiation hardened application // IEEE Transactions on Nuclear Science. 2004. V. 51. № 6. P. 3626–3630.

16. Garg R., Khatri S. P. Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations. New York: Springer, 2010. P. 194–205.

17. Soft errors in modern electronic systems / Editor M. Nicolaidis. New York: Springer, 2011. P. 35–37.

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